Integrated circuits (ICs), and especially microprocessors, are becoming increasingly complex. As a result, current microprocessors are requiring more and more power, in some cases up to 200 watts. A semiconductor package may use a package substrate to deliver power from a power supply to a semiconductor die. Current traveling through a package substrate may encounter substantial resistance. The resistance will generate heat, which can affect the performance and reliability of the die.
FIG. 1A illustrates a cross section of a typical semiconductor package. The semiconductor package 10 includes a package substrate 12, a semiconductor die 14, and an integrated heat spreader (IHS) 16. The IHS 16 dissipates heat generated by the semiconductor die 14. The semiconductor die 14 is mounted to both the package substrate 12 and the IHS 16. The IHS 16 is mounted to the package substrate 12 using an epoxy or adhesive film 18. In order to power the semiconductor die 14, an external power source drives current through conductive lines known as planes and vias in the package substrate 12. The current path 20 is shown originating from beneath the package substrate 12 and traveling through the package substrate 12 and into the semiconductor die 14.
FIG. 1B shows a more detailed view of the package substrate 12. The package substrate 12 may comprise a plastic, ceramic, silicon, etc. core having several conductive lines formed therein. The conductive lines transfer power and signals from an external power supply and external input/output (I/O) devices to the semiconductor die 14. The conductive lines of the package substrate 12 comprise planes and vias. The vias 22 and 24 can transmit current and signals vertically through the package substrate 12. The planes 26, 28, 30, and 32 can transfer current and signals horizontally through the package substrate 12. Current may enter the package substrate 12 through the bottom of the via 24. Once the current enters the package substrate 12, the current will travel horizontally along the planes 26–32 and into the via 22. Once the current reaches the via 22, it will travel through the top of the via 22 into the semiconductor die 14. Other planes and vias may be present in the package substrate 12 to provide a ground and to transmit signals to the semiconductor die 14.
As can be seen in FIG. 1B, the vias 22 and 24 have a greater cross sectional area than the planes 26–32. Further, current typically travels a shorter distance through the vias 22 and 24 than through the planes 26–32. As a result of both of these factors, most of the resistance typically found in a package substrate 12 is encountered during horizontal power delivery. In some package applications, as much as 90% of the total resistance in a package substrate 12 occurs in the planes 26–32. As a result, lateral power delivery tends to be the greater problem, since current travels well in the vertical direction.
In order to reduce the amount of lateral resistance, more planes can be added to the package substrate 12. However, the additional planes can be expensive, on the order of ten cents per plane. Further, using current technologies, the practical limit on the amount of planes that can be added to a package substrate 12 is about 200–400 micrometers (μm) of total length. Even with 400 μm of planes in a package substrate 12, there will still be significant resistance.
Another problem is that the metal used for planes 26–32 and vias 22 and 24, and the materials used for the substrate core 34 expand at different rates when heated. For example, the coefficient of thermal expansion (CTE) for copper is approximately 17 ppm/K, while the CTE for silicon is approximately 2.3–2.4 ppm/K. When the planes 26–32 are conducting current, the package substrate 12 will heat up, and the substrate core 34 and the metal will expand at different rates. This can ultimately lead to reliability problems including damage to the package substrate 12 and/or the semiconductor die 14. The problem becomes more acute when additional planes are added or more power is driven through the package substrate 12. The differing CTEs of the two materials limits the number of planes that can be added to a package substrate 12.